The inverter is one of the most fundamental elements in digital integrated circuits. The inverter is a single input, single output digital device. If a "1" is input to the input of the inverter, the output of the inverter will be a "0". Conversely, if a "0" is input to the input of the inverter, the output of the inverter will be a "1". Multiple numbers of inverters can be combined to form logical operators such as AND, OR, NAND, NOR, and other logical function blocks. Thus, in present day VLSI technology, there can be millions of inverters in a single integrated circuit performing complex logical functions.
The most common design for a CMOS inverter is shown in FIGS. 1 and 2. The CMOS inverter is comprised of one n-MOS transistor 101 and one p-MOS transistor 103. Both the n-MOS transistor 101 and p-MOS transistor 103 are enhancement mode devices with a typical threshold voltage of 0.7 volts. The output drains of the n-MOS transistor 101 and the p-MOS transistor 103 are connected together. The gate of both the n-MOS transistor 101 and the p-MOS transistor 103 are connected together to the input signal. The output of the inverter is the connection of the drains of the n-MOS and p-MOS transistors. The source of the n-MOS transistor 101 is grounded and the source of the p-MOS transistor is biased at a voltage V.sub.cc.
In operation, when the input voltage V.sub.i is "high", the n-MOS transistor 101 is on and the output V.sub.o is pulled down to ground or "low". When the input voltage V.sub.i is "low", the p-MOS transistor 103 turns on and the output V.sub.o is biased to V.sub.cc, which is considered "high".
As can be seen from FIG. 2, the prior art CMOS inverter requires two separate wells, a p-well 105 for the n-MOS transistor 101 and an n-well 107 for the p-MOS transistor 103. In addition, two control gates are necessary and an output contact is required. This makes the inverter relatively large.
What is needed is a new inverter structure that is small in size while still easy to operate and manufacture in accordance with standard CMOS manufacturing techniques.